TY - GEN
T1 - Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool
AU - Castano-Londono L.
AU - Alzate Anzola C.
AU - Marquez-Viloria D.
AU - Gallo G.
AU - Osorio G.
Y1 - 2019
UR - http://hdl.handle.net/20.500.12622/3219
AB -
ER -
@misc{20.500.12622_3219,
author = {Castano-Londono L. and Alzate Anzola C. and Marquez-Viloria D. and Gallo G. and Osorio G.},
title = {Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool},
year = {2019},
abstract = {},
url = {http://hdl.handle.net/20.500.12622/3219}
}RT Generic
T1 Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool
A1 Castano-Londono L.
A1 Alzate Anzola C.
A1 Marquez-Viloria D.
A1 Gallo G.
A1 Osorio G.
YR 2019
LK http://hdl.handle.net/20.500.12622/3219
AB
OL Spanish (121)
