Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool

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Date

2019

Author

Castano-Londono L.

Alzate Anzola C.

Marquez-Viloria D.

Gallo G.

Osorio G.

Metadata

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Source

https://www.scopus.com/inward/record.uri?eid=2-s2.0-85075682082&doi=10.1007%2f978-3-030-31019-6_5&partnerID=40&md5=0beb63940830a14de3ca0507f94350a5

URI

http://hdl.handle.net/20.500.12622/3219

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