dc.contributor.author | Castano-Londono L. | |
dc.contributor.author | Alzate Anzola C. | |
dc.contributor.author | Marquez-Viloria D. | |
dc.contributor.author | Gallo G. | |
dc.contributor.author | Osorio G. | |
dc.date.accessioned | 2020-08-28T22:27:41Z | |
dc.date.available | 2020-08-28T22:27:41Z | |
dc.date.issued | 2019 | |
dc.identifier.uri | http://hdl.handle.net/20.500.12622/3219 | |
dc.source | Scopus | |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85075682082&doi=10.1007%2f978-3-030-31019-6_5&partnerID=40&md5=0beb63940830a14de3ca0507f94350a5 | |
dc.title | Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool | spa |
dc.title.alternative | Communications in Computer and Information Science | |
dc.type | info:eu-repo/semantics/conferenceObject | |
dc.rights.accessrights | info:eu-repo/semantics/closedAccess | |
dc.identifier.doi | 10.1007/978-3-030-31019-6_5 | |
dc.relation.citationvolume | 1052 | |
dc.relation.citationstartpage | 52 | |
dc.relation.citationendpage | 63 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | |