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dc.contributor.authorCastano-Londono L.
dc.contributor.authorAlzate Anzola C.
dc.contributor.authorMarquez-Viloria D.
dc.contributor.authorGallo G.
dc.contributor.authorOsorio G.
dc.date.accessioned2020-08-28T22:27:41Z
dc.date.available2020-08-28T22:27:41Z
dc.date.issued2019
dc.identifier.urihttp://hdl.handle.net/20.500.12622/3219
dc.sourceScopus
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85075682082&doi=10.1007%2f978-3-030-31019-6_5&partnerID=40&md5=0beb63940830a14de3ca0507f94350a5
dc.titleEvaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool
dc.title.alternativeCommunications in Computer and Information Science
dc.typeinfo:eu-repo/semantics/conferenceObject
dc.identifier.doi10.1007/978-3-030-31019-6_5
dc.relation.citationvolume1052
dc.relation.citationstartpage52
dc.relation.citationendpage63
dc.type.versioninfo:eu-repo/semantics/publishedVersion


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